1. Field
The present invention generally relates to the field of self-adaptation circuit design. More specifically, the present invention relates to scaling a load device with frequency in a phase interpolator.
2. Background
Phase interpolators are important components in high-speed timing circuits, where clock and data recovery (CDR) must be performed before data can be decoded. In general, in a clock recovery system, a reference clock signal of a particular clock frequency is generated together with a number of different clock signals with the same frequency but with different phases. A conventional method to generate a number of clocks with the same frequency but with different phases is to use a voltage controlled delay loop (VCDL). Phase interpolators can be implemented to interpolate between delay stages in the VCDL to generate finer phase spacing, thus creating more clock signals. These clock signals are compared to the phase and frequency of an incoming data stream, where one or more clock signals are selected for data recovery.
FIG. 1(a) illustrates a conventional phase interpolator 100 with a0- and a1-weighted current sources. Parameters a0 and a1 refer to a number of pair transistors 111 and 121 (e.g., current tail sources), respectively, connected to each other in parallel, where an amount of current generated by differential pairs 10 and 120 varies according to the number of pair transistors 111 and 121. For instance, phase interpolator 100 can have input signals Φ0 and Φ1 that are 45° apart. The phase output of phase interpolator 100 can be varied using a current summation of differential pairs 110 and 120. That is, for a given ratio of a0:a1, a phase output from phase interpolator 100 varies. For example, as illustrated in FIG. 1(b), a ratio of a0:a1=4:4 can result in a 22.5° phase output, a ratio of a0:a1=7:1 can result in a 5.7° phase output, and a ratio of a0:a1=1:7 can result in a 39.4° phase output.
A design consideration of phase interpolator 100 is the slew rate of its phase output. For instance, as illustrated in FIG. 2, if a slew rate of input signal Φ0 is too fast, a weighted sum of the ratio a0:a1 becomes highly non-linear at output 210. In order to ensure proper phase interpolation with a relatively linear phase output (with respect to current weighting ratio a0:a1), the time constant of the phase output (τPI) should be at least twice the time separation (ΔT) between the two input phases Φ0 and Φ1 (τPI>2·ΔT). This relation sets a lower bound of the phase output time constant. Conversely, the time constant should not be too large because this reduces the frequency bandwidth and output swing of phase interpolator 100. Since the time constant is inversely proportional to frequency (τPI∝1/f), the operating frequency of phase interpolator 100 sets an upper bound of the phase output time constant. These lower and upper bound time constant constraints dictate the frequency range of phase interpolator 100.
What is needed is a method or apparatus for scaling a phase interpolator output's slew rate with operating frequency such that a wide range of operating frequency can be achieved.